The present invention relates to an integrated circuit memory including an array of flash EEPROM cells, and more particularly to circuitry for providing accurate verification in the presence of high column leakage.
A microelectronic flash or block erase Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes an array of cells which can be independently programmed and read. The size of each cell and thereby the memory are made small by omitting select transistors which would enable the cells to be erased independently. All of the cells are erased together as a block.
A memory of this type includes individual Metal-Oxide-Semiconductor (MOS) field effect transistor memory cells, each of which includes a source, drain, floating gate and control gate to which various voltages are applied to program the cell with a binary 1 or 0, or erase all of the cells as a block. The cells are connected in a rectangular array of rows and columns, with the control gates of the cells in a row being connected to a respective wordline and the drains of the cells in a column being connected to a respective bitline. The sources of the cells are connected together. This arrangement is known as a NOR memory configuration.
A cell is programmed by applying, typically, 9 volts (V) to the control gate, 5 V to the drain and grounding the source, which causes hot electrons to be injected from the drain depletion region into the floating gate. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate and create a negative charge therein which increases the threshold voltage of the cell to a value in excess of approximately 4 V.
The cell is read by applying, typically, 5 V to the control gate, 1 V to the bitline to which the drain is connected, grounding the source, and sensing the bitline current. If the cell is programmed and the threshold voltage is relatively high (e.g., 4 V), the bitline current will be zero or at least relatively low. If the cell s not programmed or erased, the threshold voltage will be relatively low (e.g., 2 V), the control gate voltage will enhance the channel, and the bitline current will e relatively high.
A cell can be erased in several ways. In one arrangement, a cell is erased by applying, typically, 12 V to the source, grounding the control gate and allowing he drain to float. This causes the electrons which were injected into the floating gate during programming to be removed by Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source. Alternatively, a cell can be erased by applying a negative voltage on the order of xe2x88x9210 V to the control gate, applying 5 V to the source and allowing the drain to float. Alternatively, a cell can be erased by applying a negative voltage on the order of xe2x88x9210 V to the control gate, and a positive voltage of the order of +10 V to the p-well.
A problem with conventional flash EEPROM cell arrangements is that due to manufacturing tolerances, some cells become overerased before other cells become erased sufficiently. Thus, after each erase procedure an erase verification process or procedure (erase verify) is conducted. Specifically, erase verify is performed cell by cell to determine if each cell in the array has a threshold above a limit (e.g., 3 V), or if the cell is xe2x80x9cundererasedxe2x80x9d. If an undererased cell is detected, an additional erase pulse is applied to the entire array. With such an erase procedure, a cell which is not undererased will also be repeatedly erased, and its floating gate may eventually acquire a threshold below zero volts. A cell with a threshold erased below zero volts is referred to as being xe2x80x9covererasedxe2x80x9d.
Overerased cells are undesirable because they create bitline leakage current during program or read procedures which can render the memory inoperative. The floating gates of the overerased cells are depleted of electrons and become positively charged. This causes the overerased cells to function as depletion mode transistors which cannot be turned off by normal operating voltages applied to their control gates, and introduces leakage during subsequent program and read operations.
On the other hand, undererased cells are also undesirable as undererased cells lead to faulty storage of data, for example. An undererased cell may be read as having a programmed binary value 1, for example, when in fact the cell is intended to have a programmed binary value 0. Thus, it is important that the erase verification procedure accurately detect the presence of an adequately erased cell. It is important that the erase verification procedure avoid a xe2x80x9cfalse verifyxe2x80x9d where an undererased cell is falsely identified as fully erased.
A problem in the past has been the bit line leakage current of overerased cells can lead to a false verify of an undererased cell during the erase verification process. More specifically, during an erase verify only one wordline which is connected to the control gates of a row of cells including the selected cell under test is held high at a time. The other wordlines are grounded. A positive voltage is applied to the drain of all of the cells in the column including the selected cell. If the threshold voltage of an unselected cell or cells in the column is zero or negative, leakage current will flow through the source, channel and drain of the unselected cell or cells and possibly result in a false verify.
This undesirable effect is illustrated in FIG. 1. The drains of a column of floating gate cell transistors T0 to Tm are connected to a bitline BL, which is itself connected to a bitline driver 1. The sources of the transistors T0 to Tm are typically connected to ground. One of the transistors T0 to Tm is selected at a time for an erase verification procedure, and a positive voltage, e.g. 5 V, is applied to its control gate which turns on the transistor. The control gates of the unselected transistors in the column are connected to ground.
As viewed in FIG. 1, 5 V is applied to the transistor T1 which turns it on. A current I1 flows through the transistor T1 from ground through its source, channel (not shown) and drain and through the bitline BL to the driver 1. Ideally, the bitline current IBL should be equal to I1, and is sensed by a sense amplifier (not shown). The sense amplifier compares the bitline current IBL to the current Iref (verify current) in a reference cell (also not shown) indicative of a sufficiently erased cell. Provided the transistor T1 is sufficiently erased, the bitline current IBL (or I1) is equal to the current Iref in the reference cell as determined by the sense amplifier. If the transistor T1 is not sufficiently erased, the bitline current IBL (or I1) is less than the current Iref as determined by the sense amplifier. Thus, it is possible to verify if the transistor T1 is sufficiently erased based on the output of the sense amplifier.
However, if one or more of the unselected transistors, e.g. the transistor T2 as illustrated in FIG. 1, is overerased, its threshold voltage will be zero or negative, and background leakage current will flow through the transistor T2 as indicated at I2. The bitline current IBL during the erase verification of transistor T1 is now no longer equal to I1, but is equal to the sum of I1 and the background leakage current I2.
In a typical flash EEPROM, the drains of a large number, for example 512, transistor cells such as illustrated in FIG. 1 are connected to each bitline (column). If a substantial number of cells on the bitline are drawing background leakage current, the total leakage current on the bitline in combination with the current from the selected cell can equal or exceed the reference cell current Iref during the erase verification process. This can result in a false verify condition where the selected cell itself is undererased yet is verified as being erased due to the contribution of the leakage current on the bitline.
In view of the aforementioned shortcomings associated with conventional flash EEPROM devices, there is a strong need in the art for an apparatus and method for providing accurate erase verification even in the presence of high column leakage. Moreover, there is a strong need in the art for an apparatus and method for performing other types of verification without false verifies even in the presence high column leakage.
The present invention provides a technique for reducing column leakage in a flash EEPROM device during a verification process, thereby preventing false verifies. The invention has application in NOR arrays or other types of arrays in which a number of cells are connected in parallel. The invention operates by reducing the leakage of the unselected cells in parallel to the selected cell or cells being verified, thereby preventing false verifies. The invention can also be used in conjunction with other techniques for reducing column leakage, such as soft programming, automatic programming disturb erase (APDE), or various other Vth compacting schemes.
During a verify process in accordance with the present invention, the current of a selected cell or cells in the array is compared to a verify reference cell current Iref. Leakage current from the unselected cells is reduced by applying a negative bias (e.g.,  less than 0 V to xe2x88x925 V) to the p-well in which the array of cells is located. The body effect of the cells will result in an increased threshold voltage (Vth) for each of the cells, thereby reducing the leakage current. By applying the same negative bias to the p-well of the reference cell, the currents of the selected cell or cells and the reference cell can be accurately compared without the accompanying leakage current from the unselected cells. In turn, this avoids false verifies during the verification process.
In accordance with one aspect of the invention, a flash memory device is provided. The flash memory device includes an array of flash memory cells formed in a p-well in a semiconductor substrate and operatively arranged in rows and columns, wherein the cells in a same row each have a control gate connected to a same corresponding wordline, the cells in a same column each have a drain connected to a same corresponding bitline, and each of the cells has a source connected to a source potential. In addition, the flash memory device includes a control circuit for verifying whether the cells have been erased. The control circuit is configured to perform the steps of: i) selecting at least one cell from among the cells in a same column by applying a high voltage to the bitline corresponding to the same column and to the wordline or wordlines correspondingly connected to the at least one cell to be selected and by applying a low voltage to the remaining wordlines correspondingly connected to the non-selected cells in the same column; ii) applying a negative voltage bias selectively to the p-well during the verify operation; iii) comparing a current through the bitline of the selected at least one cell with a current of a reference cell; and iv) verifying whether the selected at least one cell is operating properly based on the comparison.
In accordance with another aspect of the invention, a method is provided for verifying operation in a flash memory device having an array of flash memory cells formed in a p-well in a semiconductor substrate and operatively arranged in rows and columns, wherein the cells in a same row each have a control gate connected to a same corresponding wordline, the cells in a same column each have a drain connected to a same corresponding bitline, and each of the cells has a source connected to a source potential. The method includes the steps of: i) selecting at least one cell from among the cells in a same column by applying a high voltage to the bitline corresponding to the same column and to the wordline or wordlines correspondingly connected to the at least one cell to be selected and by applying a low voltage to the remaining wordlines correspondingly connected to the non-selected cells in the same column; ii) applying a negative voltage bias selectively to the p-well during the verify operation; iii) comparing a current through the bitline of the at least one selected cell with a current of a reference cell; and iv) verifying whether the selected at least one cell is operating properly based on the comparison.
To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.